Quentin Dariol

Preface

I am Quentin Dariol, a Lead Research and Development (R&D) FPGA/Hardware Design engineer currently working on many-core embedded Coarsed Grained Reconfigurable Array (CGRA) architectures at Keysom in the region of Bordeaux, France. I received in 2019 the Master’s Degree of Engineering in Electronics and Digital Technologies from the Graduate School of Engineering of Nantes Université (Polytech’Nantes) in France. I then received in 2023 the Ph.D. degree from Nantes Université for my research work on modeling and optimizing AI algorithms implementation on embedded multi-core platforms under timing and energy constraints, using SystemC.

In the rapidly evolving era of Artificial Intelligence (AI), the growth of the field increasingly depends on our ability to deploy complex algorithms on edge embedded systems (edgeAI). Yet this is a demanding challenge: such workloads typically require significant computational and memory resources, which are limited in embedded environments. Further complicating matters, these systems must operate within strict timing constraints and tight power budgets. Recognizing these challenges, I have dedicated my engineering and research efforts to optimizing the alignment between algorithms and hardware, with a particular focus on enabling efficient deployment of novel complex algorithms on embedded Systems-on-Chip (SoCs).

In short, my main skills are: FPGA/Hardware design, SystemC modeling, embedded Artificial Intelligence (edgeAI), Research & Development (R&D), technical and scientific project lead.

Profile

My professional experience

I have worked on FPGA/Hardware design in the following companies/research centers:

• Keysom, Bordeaux, France, Bordeaux France. January 2025 - Now.
• German Aerospace Center (DLR), Oldenburg, Germany. March 2022 - December 2024.
• IETR laboratory, Nantes, France. September 2020 - February 2022.
• Thales, Bordeaux, France, February 2019 - June 2020.

My academic curriculum

I have the following academic curriculum:

• Ph.D. in Electronics, Nantes Université, France. Defended on November 27th, 2023.
  • The Ph.D. thesis is available here: https://theses.hal.science/tel-04390337v1.
  • The proposed flow and results are available in this open-source Git repository: https://github.com/qdariol/pssim4ai.
• Master’s Degree of Engineering in Electronics and Digital Technologies, Graduate School of Engineering of Nantes Université (Polytech’Nantes), France. Graduated in 2019.
• Intensive preparation courses for the competitive engineering school entrance exam (CPGE MathSup/MathSpé), Bordeaux, France.

My skills

My skill-set includes:

• Research, specification, development, verification and documentation of FPGA designs.
  • Hardware Description Languages: SystemVerilog, Verilog, VHDL, Amaranth HDL, verification with UVM.
• Electronic System Level (ESL) modeling: SystemC TLM.
• EdgeAI: implementation and optimization of complex AI algorithms on FPGA and embedded systems.
• Micro-architecture, RISC-V Instruction-Set Architecture (ISA).
• Drivers and bare-metal Software development in C/C++.
• Automatization and scripting: Python, Jinja, shell, TCL.
• Technical and scientific project lead.
• Fluent in French, good command in English and working knowledge in German.

Research projects contributed

I have contributed in the following research projects:

• CREA: This project funded by the European Union is led between Keysom, CATIE and SERMA ID MOS. It aims at proposing novel System-on-Chips (SoC) composed of a customized RISC-V processor coupled with optimized AI accelerators, delivering higher performance while significantly reducing energy consumption. In the scope of CREA, Keysom delivers RISC-V processors coupled with CGRA accelerators.
  • Role: Main contributor, scientific and hardware design project lead on the CGRA R&D in Keysom.
  • Contributed in: 2025 to 2026.
• ADMIRE: German Aerospace Center (DLR) project aimed at proposing novel techniques and technologies for satellite constellations with a focus on space-based radar systems,
  • Role: Scientific project lead and coordinator of contributors from several DLR institutes, main responsible of a work package focused on the R&D of energy-efficient neuromorphic on-board computers for space applications.
  • Contributed in: 2024.
• Scale4Edge: Joint project funded by the BMBF (Federal Ministry of Education and Research), which aims to significantly reduce the currently relatively long development times and high development costs of application-specific edge components (platform concept).
  • Role: R&D participant.
  • Contributed in: 2022 to 2023.
• pSSim4AI: Funding from the Wise consortium obtained for my Ph.D. work at Nantes Université. This project aims at enabling the collaboration between the IETR lab of Nantes Université and the DLR to research and develop a workflow for modeling and analyzing the extra-functional properties (execution time, energy) of Artificial Neural Networks (ANNs) on multi-core architectures.
  • Role: Main scientific and technical contributor as Ph.D. student.
  • Duration: September 2020 to February 2022.
• SAFEPOWER: Safe and secure mixed-criticality systems with low power requirements. Funded by the European Union (EU).
  • Role: Intern in OFFIS.
  • Contributed in: 2018.

Scientific publications

International journal article:

• JSA’2026: A Measurement-Based Calibration Approach for Highly Scalable Timing and Energy Modeling of EdgeAI Multi-Core Systems
  • Journal: Elsevier International Journal of Systems Architecture
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
  • The presented flow and results are publicly available on this open-source Git repository: https://github.com/qdariol/pssim4ai

Lectures in international conferences and workshops:

• DASIP’2026: MultiGRA: Expanding the CGRA Design Space with a Mixed-Granularity Approach - Conference/workshop: International Workshop on Design and Architectures for Signal and Image Processing (DASIP)
  • Authors: Léo Pajot, Quentin Dariol, Jérémie Crenne, Simon Rokicki and Bertrand Le Gal.
• RAPIDO’2023: Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms - Conference/workshop: International Workshop on Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO)
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• SAMOS’2022: A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms
  • Conference/workshop: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Ph.D. thesis:

• PhDThesis’2023: Early Timing and Energy Prediction and Optimization of Artificial Neural Networks on Multi-Core Platforms, Nantes Université
  • Author: Quentin Dariol

Posters & abstracts:

• GDRSOC’2024: Low Power and High-Throughput LUT-based Accelerator Architecture for Distributed CNN Inference at the Edge
  • Authors: Quentin Dariol, Domenik Helms.
• GRETSI’2023: Early Performance and Energy Prediction of Neural Networks Deployed on Multi-Core Platforms
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• GDRSOC’2022 Hybrid Performance Prediction Models for Fully-Connected Neural Networks on MPSoC
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• GDRSOC’2021: A Measurement-based Performance Evaluation Framework for Neural Networks on MPSoCs
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Technical report:

• TechReport’2022 Setup of an Experimental Framework for Performance Modeling and Prediction of Embedded Multicore AI Architectures
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Provided teachings

I participated in giving the following teachings (practical sessions) at the Electronics and Digital Technologies Department of the Graduate School of Engineering of Nantes Université (Polytech’Nantes):

• Hardware/Software (HW/SW) System Co-Design
  • Master 2 level, taught in 2021-2022 and 2020-2021. This course teaches a specification, design and implementation methodology of embedded systems architectures, combining the Hardware and Software aspect. Various technologies are used in this course: system specification and design in the Intel Confluent Studio software, design and test of HW/SW applications on MPSoCs (FPGA) using Xilinx Vivado and Vitis (SDK).
• Digital Circuits Design,
  • Master 1 level, taught in 2021-2022. This course teaches a methodology of specification, design and verification of applications implemented on embedded systems. This course focuses on the example of a Local Interconnect Network (LIN) receiver circuit. Students use HDL Designer along with RTL simulation to describe and validate the design.
• Real-Time Embedded Software,
  • Master 1 level, taught in 2020-2021. In this course, students learn to develop embedded applications with real time constraints. They use the Real Time Operating System (RTOS) VxWorks in the tool Wind River Workbench.
• Technical projects supervision,
  • Master 2 level, taught in 2021-2022 and 2020-2021. This involves the supervision of students working on a embedded systems engineering industrial or research project. Students dedicate one day per week to their technical project during one semester. Example of projects supervised: Development of Convolutional Neural Network (CNN) applications on embedded multi-core platforms on FPGA.

Other references

Find out more there:

• LinkedIn profile
• ORCid