Quentin Dariol

Preface

I am Quentin Dariol, a confirmed level (>6 years of experience) Research and Development (R&D) FPGA and embedded systems engineer. I am currently working on the specification and development of embedded many-core architectures in the form of Coarsed-Grained Reconfigurable Arrays (CGRAs) in Keysom in the region of Bordeaux, France.

In the rapidly evolving era of Artificial Intelligence (AI), the growth of the field increasingly depends on our ability to deploy complex algorithms on edge embedded systems (edgeAI). Yet this is a demanding challenge: such workloads typically require significant computational and memory resources, which are limited in embedded environments. Further complicating matters, these systems must operate within strict timing constraints and tight power budgets. Recognizing these challenges, I have dedicated my engineering and research efforts to optimizing the alignment between algorithms and hardware, with a particular focus on enabling efficient deployment of novel complex algorithms on embedded Systems-on-Chip (SoCs).

Profile

My professional experience

I have worked on the R&D of FPGA designs in the following companies/research centers:

• Keysom, Bordeaux, France, Bordeaux France. January 2025 - Now.
• German Aerospace Center (DLR), Oldenburg, Germany. March 2022 - December 2024.
• IETR laboratory, Nantes, France. September 2020 - February 2022.
• Thales, Bordeaux, France, February 2019 - June 2020.

My academic curriculum

I have the following academic curriculum:

• PhD in Electronics, Nantes Université, France. Defended on 27.11.2023.
• Master of Engineering in Electronics and Digital Technologies, Graduate School of Engineering of Nantes Université, France. Graduated in 2019.
• Intensive preparation courses for the competitive engineering school entrance exam (CPGE MathSup/MathSpé), Bordeaux, France.

My skills

My skill-set includes:

• Research, specification, development, verification and documentation methodology of FPGA designs and embedded systems,
  • Hardware Description Languages: SystemVerilog, Verilog, VHDL, Amaranth HDL, verification with UVM.
• Electronic System Level (ESL) modeling - SystemC TLM,
• EdgeAI: deployment and optimization of AI algorithms on FPGA and embedded systems.
• Micro-architecture, RISC-V Instruction-Set Architecture (ISA),
• Drivers and bare-metal Software development in C/C++,
• Automatization and scripting: Python, Jinja, shell, TCL,
• Technical and scientific lead of projects,
• Fluent in French, good command in English and working knowledge in German.

Visit my my LinkedIn profile for more details and getting in touch.

Scientific publications

Projects:

• pSSim4AI is the Git repository containing the SystemC-based modeling flow proposed and developed during my PhD. It enables fast yet accurate prediction of time and energy for neural networks on multi-core platforms.
• ADMIRE: I worked for one year as scientific and technical lead for the project ADMIRE at DLR, on a work package focused on the developement of energy-efficient neuromorphic on-board computers.

PhD thesis:

• PhDThesis’2023: Early Timing and Energy Prediction and Optimization of Artificial Neural Networks on Multi-Core Platforms, Nantes Université
  • Author: Quentin Dariol

International journal article:

• JSA’2026: A Measurement-Based Calibration Approach for Highly Scalable Timing and Energy Modeling of EdgeAI Multi-Core Systems
  • Journal: Elsevier Journal of Systems Architecture
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Lectures in international conferences and workshops:

• DASIP’2026: MultiGRA: Expanding the CGRA Design Space with a Mixed-Granularity Approach - Conference/workshop: Workshop on Design and Architectures for Signal and Image Processing (DASIP)
  • Authors: Léo Pajot, Quentin Dariol, Jérémie Crenne, Simon Rokicki and Bertrand Le Gal.
• RAPIDO’2023: Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms - Conference/workshop: Workshop on Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO)
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• SAMOS’2022: A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms
  • Conference/workshop: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Posters & abstracts:

• GDRSOC’2024: Low Power and High-Throughput LUT-based Accelerator Architecture for Distributed CNN Inference at the Edge
  • Authors: Quentin Dariol, Domenik Helms.
• GRETSI’2023: Early Performance and Energy Prediction of Neural Networks Deployed on Multi-Core Platforms
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• GDRSOC’2022 Hybrid Performance Prediction Models for Fully-Connected Neural Networks on MPSoC
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.
• GDRSOC’2021: A Measurement-based Performance Evaluation Framework for Neural Networks on MPSoCs
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Technical report:

• TechReport’2022 Setup of an Experimental Framework for Performance Modeling and Prediction of Embedded Multicore AI Architectures
  • Authors: Quentin Dariol, Sébastien Le Nours, Sébastien Pillement, Ralf Stemmer, Domenik Helms and Kim Grüttner.

Provided teachings

I had the pleasure to give the following teachings (practical sessions) at the Electronics and Digital Technologies Department of the Graduate School of Engineering of Nantes Université (Polytech’Nantes):

• Hardware/Software (HW/SW) System Co-Design
  • Master 2 level, taught in 2021-2022 and 2020-2021. This course teaches a specification, design and implementation methodology of embedded systems architectures, combining the Hardware and Software aspect. Various technologies are used in this course: system specification and design in the Intel Confluent Studio software, design and test of HW/SW applications on MPSoCs (FPGA) using Xilinx Vivado and Vitis (SDK).
• Technical projects,
  • Master 2 level, taught in 2021-2022 and 2020-2021. This involves the supervision of students working on a embedded systems engineering industrial or research project. Students dedicate one day per week to their technical project during one semester. Example of projects supervised: Development of Convolutional Neural Network applications on an embedded multi-core platform on FPGA.
• Digital Circuits Design,
  • Master 1 level, taught in 2021-2022. This course teaches a methodology of specification, design and verification of applications implemented on embedded systems. This course focuses on the example of a Local Interconnect Network (LIN) receiver circuit. Students use HDL Designer along with RTL simulation to describe and validate the design.
• Real-Time Embedded Software,
  • Master 1 level, taught in 2020-2021. In this course, students learn to develop embedded applications with real time constraints. They use the Real Time Operating System (RTOS) VxWorks in the tool Wind River Workbench.

Other references

Find out more there:

• LinkedIn profile
• ORCid.
• Zenodo.
• Publications available on HAL - Archives Ouvertes.
• {ublications available on e-Lib (DLR archives).