Preface
Hi! My name is Quentin Dariol. I am a confirmed research and development engineer in the field of embedded hardware architectures. I am currently working on embedded hardware architectures and associated compilers for the company Keysom, in the region of Bordeaux, France.
In the rapidly evolving era of Artificial Intelligence (AI), the growth of the field increasingly depends on our ability to deploy complex algorithms on embedded systems. Yet this is a demanding challenge: AI workloads typically require significant computational and memory resources, which are often limited in embedded environments. Further complicating matters, these systems must operate within strict timing constraints and tight power budgets—conditions that are not naturally suited to AI applications. Recognizing these challenges, I have dedicated my research and engineering efforts to optimizing the alignment between algorithms and hardware, with a particular focus on enabling efficient deployment of AI algorithms on embedded Systems-on-Chip (SoCs).
My professional experience
Note: you will also be able to go through this on my LinkedIn profile
- Research and development engineer, Keysom, Bordeaux France. January 2025 - Now.
- Technology watch on edge hardware accelerator architectures. Research and developement of Coarsed-Grain Reprogrammable Architecture (CGRA) Hardware and Compiler.
- Researcher, German Aerospace Center (DLR), Institute, Oldenburg, Germany. March 2022 - December 2024
- Management of a work package involving participants from several DLR institutes, for the research and development of energy-efficient neuromorphic on-board computers for satellite constellations, in the scope of the DLR ADMIRE project.
- Development of a minimal latency and power consumption hardware accelerator architecture for edge transformer and Convolutional Neural Networks (CNNs) inference. Research led in the scope of ADMIRE.
- Research in the scope of my PhD work: timing and energy optimization methodology of Artificial Neural Networks (ANNs) on multi-core platforms.
- Researcher, IETR UMR CNRS 6164, Nantes Université, France. September 2020 - February 2022
- Research in the scope of my PhD work: timing and energy optimization methodology of Artificial Neural Networks (ANNs) on multi-core platforms.
- FPGA engineer, Thales, Mérignac, France. February 2019 - June 2020
- Verification and documentation of a dedicated avionics Graphical Processing Unit (GPU) architecture on FPGA.
- Porting of a FPGA design on Intel Cyclone V SoC with performance enhancement. Implementation, verification and validation through ModelSim (RTL) simulation and physical tests.
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My academic curriculum
- PhD in Electronics, Nantes Université, France. Defended on 27.11.2023.
- Master of Engineering in Electronics and Digital Technologies, Graduate School of Engineering of Nantes Université, France. Graduated in 2019.
- Intensive preparation courses for the competitive engineering school entrance exam (CPGE MathSup/MathSpé), Bordeaux, France.
Provided teachings
I had the pleasure to give the following teachings (practical sessions) at the Electronics and Digital Technologies Department of the Graduate School of Engineering of Nantes Université (Polytech’Nantes):
- Hardware/Software (HW/SW) System Co-Design
- Master 2 level, taught in 2021-2022 and 2020-2021. This course teaches a specification, design and implementation methodology of embedded systems architectures, combining the Hardware and Software aspect. Various technologies are used in this course: system specification and design in the Intel Confluent Studio software, design and test of HW/SW applications on MPSoCs (FPGA) using Xilinx Vivado and Vitis (SDK).
- Technical projects,
- Master 2 level, taught in 2021-2022 and 2020-2021. This involves the supervision of students working on a embedded systems engineering industrial or research project. Students dedicate one day per week to their technical project during one semester. Example of projects supervised: Development of Convolutional Neural Network applications on an embedded multi-core platform on FPGA.
- Digital Circuits Design,
- Master 1 level, taught in 2021-2022. This course teaches a methodology of specification, design and verification of applications implemented on embedded systems. This course focuses on the example of a Local Interconnect Network (LIN) receiver circuit. Students use HDL Designer along with RTL simulation to describe and validate the design.
- Real-Time Embedded Software,
- Master 1 level, taught in 2020-2021. In this course, students learn to develop embedded applications with real time constraints. They use the Real Time Operating System (RTOS) VxWorks in the tool Wind River Workbench.
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